With ever decreasing feature size of semiconductor devices, the potential distribution in the device during operation and related properties such as the electrical field distribution and the extent of space-charge regions next to junctions are of great interest. Knowledge of these quantities with nanometer resolution becomes crucial for activities such as TCAD device simulator development and also for manufacturing process evaluation. Simulation software for submicron devices needs reliable data provided by characterization techniques for calibration. Measurement techniques therefore must be simple, have a high spatial resolution and sensitivity, have to be applicable to both conducting and non-conducting samples, and be affected as little as possible by the corrections caused by the measuring instruments. A semiconductor element should be subjected to as few as possible preparation steps in order to allow for such measurements. It is furthermore a specific need for quality control during production and development of semiconductor elements to determine the spatial distribution of the electrically active charge carriers therein. In particular, after annealing of doped semiconductor elements it is uncertain which part of the dopants is of significance electrically and what is the actual spatial distribution of these charge carriers in the semiconductor element. Submicron device development and fabrication hinges on the tight control of dopant incorporation and (re)distribution during the whole fabrication process. Facing the increasing costs for processing, extensive usage of process and device simulation programs (TCAD) has become a standard in technology development. However since advanced processes contain numerous less well characterized processing steps (like short time anneals, transient diffusion, stress induced diffusion, 2D-diffusion . . . ), models are not yet completely predictive. Calibration of TCAD-tools and further model development are therefore essential activities for semiconductor companies involved in deep submicron technology. An important restriction in the successful application of this strategy is the availability of suitable characterization methods. With decreasing device dimensions the requirements posed on the analysis tools have increased from moderate requirements on 1D-depth resolution and sensitivity applied to simple test structures to very stringent requests related to 2D-resolution (nm!), quantification accuracy (2-5%) and the capability to probe directly on devices. Concurrent with the TCAD-needs are the demands from failure analysis for high spatial resolution analysis of devices.
Scanning proximity microscopes are known in the prior art. Said microscopes are capable of imaging the surface of a substrate with atomic resolution. Conventional scanning proximity microscopes provide signals which correspond to changes in the topography of the sample under investigation. Scanning probe technology already has gained wide access in the semiconductor fabrication particularly for surface roughness (with sub-nm sensitivity) and dimensional metrology. The extension from a pure topographical measurement towards a more functional analysis (carrier or potential profiling) by the (additional) acquisition of a relevant electrical signal might lead to a method satisfying the TCAD- and failure analysis needs in terms of the required 2D-resolution, electrical information and applicability to devices.
Techniques are known in the prior art by which the potential distribution of a semiconductor element can be measured. The paper Scanning Tunneling Potentiometry, Appl. Phys. Lett. 48, 514 (1986) by Muralt and Pohl discloses a method for measuring the potential distribution on conductor/semiconductor elements by using a scanning tunneling microscope (STM). In said method the different frequencies constituting the tunneling current between a conducting tip and the semiconducting/conducting element under investigation are separated in order to obtain electrical potential characteristics. Said method suffers from the disadvantage that the STM-tip does not make contact with the semiconducting/conducting element under investigation. Further, the measured potential distribution is disturbed by the tunneling current, injected in the semiconducting/conducting element under investigation. Said method furthermore is sensitive to the presence of contaminants present on the semiconducting/conducting element under investigation. M. Anders et al., in the paper Potentiometry for Thin-Film Structures using Atomic Force Microscopy, J. Vac. Sci. Technol.A8, 394 (1990) discloses a STM/AFM based noncontact potential measurement. Said method is disturbed by the tunneling current, injected in the semiconducting/conducting element under investigation and is sensitive to the presence of contaminants present on the semiconducting/conducting element under investigation. U.S. Pat. No. 5,122,739 discloses a method and apparatus for measuring node voltages on integrated circuits. Said method and apparatus are based on the STM-technique. Nonnenmacher et al. disclose in the paper Kelvin Probe Force Microscopy, Appl. Phys. Lett. 58, 2921 (1991) a method for measuring the contact potential difference between different materials using Kelvin Probe Force Microscopy. The prior art fails to disclose a method to measure the electrical potential in semiconductor element without disturbing said electrical potential. The cited references fail to disclose a method to measure the electrical potential in a semiconductor element that is insensitive to the presence of contaminants on the surface of the semiconducting/conducting elements under investigation. The cited references fail to disclose a method that is a method that allows simultaneous measurements of the topography and the potential distribution of semiconductor elements and related/derived characteristics thereof using a scanning proximity microscope in contact mode.